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CPLD Operational Modes:
The CPLD is controlled with five addressable registers.
TABLE 2. CPLD Register Description
Bit-
Address (hex)
0x40
width
8
Read/Write
Read Only
Description
Version Description
Function
Returns current revision level of the
CPLD programming when Peeked.
0x41
8
Read Only
Device ID Register
Returns the device ID when
Peeked.
0x42
8
Read Only
Status Register
MPI I/O implemented. Register cur-
rently not used.
0x43
8
Read/Write
Configuration Register 0
Lower 4 bits assigned to Feedback
Sample Selector. MPI I/O imple-
mented; core function not imple-
mented
0x44
8
Read/Write
Configuration Register 1
Selects the output which is routed
back in to FB<19:0> and the signal
source for FBCLK. See Table 3 for
additional details.
There are eight CPLD operational modes selectable in
control word 0x44. These modes are as shown in Table 3
and control the input source for FB<19:0> and FBCLK.
TABLE 3. CPLD Feedback Operational Modes
CPLD U2
1. Install the parallel port JTAG programming cable XILINX
Model Number DLC5, Parallel Cable III from the
computer parallel port to the ISL5239EVAL1 connector
J9 as follows:
0x44
0x00 (default)
0x01
0x02
Source for FB<19:0>
Hi-z
IOUT<17:0>
QOUT<17:0>
Source for FBCLK
Hi-z
CPLD_CLK0 (system
clock)
CPLD_CLK0
? TMS to J9-7
? TCK to J9-9
? TDI to J9-12
? TDO to J9-14
0x03
IOUT<17:8>,QOUT<17:8> CPLD_CLK0
? VCC to J9-19
0x04
0x05
0x06
0x07
Connector J8 (Ext. FDBK)
Connector J8 (Ext. FDBK)
Connector J8 (Ext. FDBK)
Connector J8 (Ext. FDBK)
J8-19
J8-19
CPLD_CLK0
CPLD_CLK0
? GND to J9-20.
2. Launch the Xilinx Device Programming iMPACT software
or any similar device programming software.
3. Select ‘cancel’ on the ‘Operation Mode Selection’ dialog
box.
CPLD and FPGA Programming
The evaluation board contains two programmable devices
which are configured to support normal device evaluation
and operation. These devices can be modified and re-
programmed to meet a user ’s needs via the a JTAG
programming interface J9. U2 is a Xilinx XC95288XL-
6PQ208C CPLD, and is required for basic board functions.
U3 is a Xilinx XC18V01VQ44C SPROM which supports
optional FPGA functions. The Verilog for both of these
devices is downloadable from the product page for the
evaluation board, and the devices can be re-programmed
utilizing the following general instructions.
4. Apply power to the CCA.
5. Right click on the main screen and select ‘Initialize
Chain.’
6. This will identify the device and pop-up a file selection
window. Navigate to the desired .jed file.This will allow
the JTAG Programmer to display the TDI - device - TDO
chain, specifying .jed file as the programing file.
7. Highlight the XC95288XL with the cursor, right click, and
select ‘Program.’ In the Program Options dialog box,
check ‘Erase Before Programming’ and ‘Program’, then
‘OK’.
8. Verify all programming actions are completed
successfully. Troubleshoot the J9 JTAG to U2 path if
programming is unsuccessful.
5
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